The invention relates generally to integrated circuits and semiconductor device fabrication and, in particular, to structures that provide electrostatic discharge (ESD) protection and methods for fabricating a structure that provides ESD protection.
An integrated circuit may be exposed to random ESD events that can direct potentially large and damaging ESD currents to the integrated circuits of the chip. An ESD event refers to an electrical discharge of a current (positive or negative) over a short duration and during which a large amount of current is directed to the integrated circuits. The high current may originate from a variety of sources, such as the human body, a machine component, a carrier, etc.
Precautions may be taken to avoid causing ESD events or to protect an integrated circuit from ESD events. One such precaution is to incorporate an ESD prevention circuit into the chip. The ESD protection circuit can prevent damage to sensitive devices of the integrated circuit during post-manufacture chip handling and after chip installation on a circuit board or other carrier. If an ESD event occurs, the ESD protection circuit triggers an ESD protection device, such as a silicon-controlled rectifier, to enter a low-impedance state that conducts ESD current to ground and away from the sensitive devices of the integrated circuit. The ESD protection device is clamped in its low-impedance state until the ESD current is drained and the ESD voltage is discharged to an acceptable level.
Improved structures that provide ESD protection and methods for fabricating a structure that provides ESD protection are needed.